1. Field of the Invention
The present invention generally relates to a timing signal delay circuit. More particularly, the invention is concerned with a delay circuit for delaying an input timing pulse signal with twice as high resolution as that of data set for the delay.
2. Description of the Prior Art
For having a better understanding of the present invention, a timing signal delay circuit known heretofore will be considered in some detail by referring to FIG. 3 of the accompanying drawings.
In FIG. 3, a reference numeral 1 denotes a counter, 2 denotes a detection circuit for detecting all "0s" making appearance at the output terminals of the counter 1, and a numeral 3 denotes a first flip-flop (FF) circuit. Further, a reference numeral 11 designates an input timing pulse as well as an input terminal therefor, 12 designates a first clock signal, 13 designates a second clock signal, 21 to 24 designate delay setting data placed in the counter 1, and a numeral 16 designates a delayed timing pulse signal output. The counter 1 shown in FIG. 3 is implemented as a down-counter and placed initially with the delay setting data 21 to 24.
In operation, when the timing pulse signal 11 is supplied, the counter 1 responds to the first clock pulse signal 12 to start the count-down operation of the delay setting data placed therein. When it is detected by the detection circuit 2 that all the outputs of the counter 1 becomes "0s", the timing pulse signal is outputted in response to the rising edge of the second clock pulse 13.
More specifically, reference is made to FIG. 4 which is a timing chart for illustrating the operation of the timing pulse signal delay circuit shown in FIG. 3.
In FIG. 4, there is shown at (a) a waveform of the input timing pulse signal 11. A waveform of the first clock signal 12 is shown at (b). The delay setting data 21 to 24 placed in the down-counter 1 are illustrated at (c) to (f), respectively. In the case of this example, the delay setting data is assumed to be "0110".
Upon application of the input timing pulse signal 11, the down-counter 1 starts the down-count operation in synchronism with the first clock pulse signal 21, as shown in FIG. 4 at (g) to (j). When all the delay data 21 to 24 are counted down to "0s", the detection circuit 2 produces an output pulse signal of a waveform shown at (k), which is applied to the flip-flop circuit 3. At the timing of the rising edge of the second clock pulse signal 13, the flip-flop circuit 3 outputs the delayed timing pulse signal 16, as shown at (m) in FIG. 4. In this manner, the timing pulse signal delay circuit shown in FIG. 3 delays the output timing pulse signal 16 shown at (m) in FIG. 4 relative to the input timing pulse signal 11 shown at (a) with the amount of delay determined by the delay setting data placed in the counter 1.
At this juncture, it should be mentioned that the counter 1 shown in FIG. 3 may be implemented as an up-counter as well.